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ICSpider

An automatic tool to streamline the test-chip design and optimize for product diagnostics

Overview

ICSpider is a design tool that automates the whole design process of product debug test chip.
In a real product with complex layout and varied environment conditions, there may be differences between test keys used during process development stage and the real products. These differences may induce gaps of electrical characteristics between test keys and real produce devices, which in turn may cause yield or performance issues.
ICSpider helps to address this gap and support product diagnostics through the least costly solution, which keeps device relevant layers (FEOL/MOL) intact to preserve product relevance but only modifies BEOL connection layer. It is beneficial to capture electrical read-out from real product at the device level to guide the improvement of product yield and performance metrics such as speed and power consumption.

Electrical test based on product layout

Change BEOL connection layer with FEOL/MOL unchanged to connect critical devices to PAD directly, which ensures the electrical read-out from real product at the device level

Automatic process for BEOL modification

The whole process mainly includes flexible method to define target device, powerful algorithm to select target device, powerful algorithm to realize target device identification, pin extraction, and automatic routing

Main Features

Support device auto-extraction from product layout
Built-in database engine MySQL to store and manage device lists
Flexible method to define target device
Powerful algorithm to select target device
Support automatic target device identification and pin extraction
Powerful algorithm to realize auto-route
Built-in error checking for connection
Built-in DRC for error-free design
Support automatic LVS verification
Proven flow optimized for multiple technologies with partners
Support multi-user collaborative work mode

Applications

In one project, a product chip based test chip customized by ICSpider was used to capture the actual performance of a large number of devices from product chip. Among millions of devices, some abnormal devices were found to deviate from the model and run fast.
By analyzing the design layout, the commonality of design characteristics of those devices and the physical causes of performance deviation were found.
The project team feedback findings from ICSpider to the technical team of foundry for targeted process troubleshooting; at the same time, the chip reaches low-power consumption while maintaining the speed through improving the layout design, generating new photomasks and directly adjusting the corresponding device characteristics.